Register Summary: Pwm; Register Details: Pwm - Analog Devices ADuCM310 Hardware Reference Manual

ADuCM310 Hardware Reference Manual

REGISTER SUMMARY: PWM

Table 273. PWM Register Summary
Address Name
0x40024000 PWMCON0
0x40024004 PWMCON1
0x40024008 PWMICLR
0x40024010 PWM0COM0
0x40024014 PWM0COM1
0x40024018 PWM0COM2
0x4002401C PWM0LEN
0x40024020 PWM1COM0
0x40024024 PWM1COM1
0x40024028 PWM1COM2
0x4002402C PWM1LEN
0x40024030 PWM2COM0
0x40024034 PWM2COM1
0x40024038 PWM2COM2
0x4002403C PWM2LEN
0x40024040 PWM3COM0
0x40024044 PWM3COM1
0x40024048 PWM3COM2
0x4002404C PWM3LEN

REGISTER DETAILS: PWM

PWM Control Register
Address: 0x40024000, Reset: 0x0012, Name: PWMCON0
Table 274. Bit Descriptions for PWMCON0
Bits Bit Name
15 SYNC
14 PWM7INV
13 PWM5INV
12 PWM3INV
11 PWM1INV
10 PWMIEN
9 ENA
[8:6] PWMCMP
5 POINV
4 HOFF
Description
PWM control register
ADC conversion start and trip control register
Hardware trip configuration register
Compare Register 0 for PWM0 and PWM1
Compare Register 1 for PWM0 and PWM1
Compare Register 2 for PWM0 and PWM1
Period value register for PWM0 and PWM1
Compare Register 0 for PWM2 and PWM3
Compare Register 1 for PWM2 and PWM3
Compare Register 2 for PWM2 and PWM3
Period value register for PWM2 and PWM3
Compare Register 0 for PWM4 and PWM5
Compare Register 1 for PWM4 and PWM5
Compare Register 2 for PWM4 and PWM5
Period value register for PWM4 and PWM5
Compare Register 0 for PWM6 and PWM7
Compare Register 1 for PWM6 and PWM7
Compare Register 2 for PWM6 and PWM7
Period value register for PWM6 and PWM7
Description
Set to enable PWM synchronization from the SYNC pin of the PWM.
0: ignore transition from the SYNC pin.
1: all PWM counters are reset on the next clock cycle after detection of a
falling edge from the SYNC pin.
Set to invert PWM7 output.
Set to invert PWM5 output.
Set to invert PWM3 output.
Set to invert PWM1 output.
Set to enable interrupts for PWM.
When HOFF = 0 and HMODE = 1, this bit serves as enable for Pair 0 and Pair 1.
0: disable Pair 0 and Pair 1.
1: enable Pair 0 and Pair 1.
PWM clock prescaler. Sets HCLK divider.
000: HCLK/2.
001: HCLK/4.
010: HCLK/8.
011: HCLK/16.
100: HCLK/32.
101: HCLK/64.
110: HCLK/128.
111: HCLK/256.
Set to invert PWM outputs for Pair 0 and Pair 1 when PWM is in H-bridge mode.
Set to turn off the high-side for Pair 0 and Pair 1 when PWM is in H-bridge mode.
Rev. C | Page 181 of 192
UG-549
Reset Access
0x0012 RW
0x0000 RW
0x0000 RW1C
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x1 RW