Table Of Contents - Analog Devices ADuCM310 Hardware Reference Manual

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TABLE OF CONTENTS

Scope .................................................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Using the ADuCM310 Hardware Reference Manual .................. 5
Number Notations ........................................................................ 5
Register Access Conventions ...................................................... 5
Acronyms and Abbreviations ..................................................... 5
Introduction to the ADuCM310 .................................................... 6
Main Features of the ADuCM310 .............................................. 7
Memory Organization ................................................................. 8
Clocking Architecture ...................................................................... 9
Clocking Architecture Features .................................................. 9
Clocking Architecture Block Diagram ...................................... 9
Clocking Architecture Overview.............................................. 10
Clocking Architecture Operation............................................. 10
Register Summary: Clock Architecture ................................... 10
Register Details: Clock Architecture ........................................ 10
Power Management Unit ............................................................... 14
Power Management Unit Features ........................................... 14
Power Management Unit Overview ......................................... 14
Power Management Unit Operation ........................................ 14
Code Examples ........................................................................... 15
Register Summary: Power Management Unit ........................ 16
Register Details: Power Management Unit ............................. 16
ARM Cortex-M3 Processor .......................................................... 17
ARM Cortex-M3 Processor Features....................................... 17
ARM Cortex-M3 Processor Overview .................................... 18
ARM Cortex-M3 Processor Operation ................................... 18
ARM Cortex-M3 Processor Related Documents ................... 18
ADC Circuit .................................................................................... 19
ADC Circuit Features ................................................................ 19
ADC Circuit Block Diagram..................................................... 19
ADC Circuit Overview .............................................................. 19
ADC Circuit Operation ............................................................. 20
ADC Transfer Function ............................................................. 20
ADC Typical Setup Sequence ................................................... 22
ADC Input Buffer ....................................................................... 22
ADC Internal Channels ............................................................. 23
ADC Support Circuits ............................................................... 24
Register Summary: ADC Circuit ............................................. 27
ADuCM310 Hardware Reference Manual
Register Details: ADC Circuit .................................................. 28
Register Summary: Additional Registers ................................ 32
Register Details: Additional Registers ..................................... 32
IDACs ............................................................................................... 34
IDAC Features ............................................................................ 34
IDAC Block Diagram ................................................................. 34
IDAC Overview .......................................................................... 34
Register Summary: IDAC ......................................................... 40
Register Details: IDAC............................................................... 40
VDACs ............................................................................................. 46
VDAC Features ........................................................................... 46
VDAC Block Diagram ............................................................... 46
VDAC Overview ........................................................................ 46
VDAC Operation ....................................................................... 47
Register Summary: VDAC ........................................................ 49
Register Details: VDAC ............................................................. 49
System Exceptions and Peripheral Interrupts............................. 56
Cortex-M3 and Fault Management ......................................... 56
External Interrupt Configuration ............................................ 59
Register Summary: External Interrupts .................................. 59
Register Details: External Interrupts ....................................... 60
Low Voltage Analog Die Interrupt Configuration................. 63
Register Summary: Low Voltage Die Interrupts .................... 63
Register Details: Low Voltage Die Interrupts ......................... 64
Reset ................................................................................................. 65
Reset Features ............................................................................. 65
Reset Operation .......................................................................... 65
Register Summary: Reset .......................................................... 65
Register Details: Reset ............................................................... 66
DMA Controller ............................................................................. 67
DMA Features ............................................................................. 67
DMA Overview .......................................................................... 67
DMA Operation ......................................................................... 67
Interrupts ..................................................................................... 68
DMA Priority .............................................................................. 68
Channel Control Data Structure .............................................. 68
Control Data Configuration ..................................................... 69
DMA Transfer Types (CHNL_CFG[2:0]) ............................... 70
Address Calculation ................................................................... 72
Aborting DMA Transfers .......................................................... 72
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