Register Summary: Wake-Up Timer; Register Details: Wake-Up Timer - Analog Devices ADuCM310 Hardware Reference Manual

UG-549
Interrupts/Wake-Up Signals
An interrupt is generated when the counter value corresponds to any of the compare points or full scale in free running mode. The timer
continues counting or is reset to zero.
The wake-up timer generates five maskable interrupts. They are enabled in the T4IEN register. Interrupts can be cleared by setting the
corresponding bit in the T4CLRI register.
Note that it takes two 32 kHz clock cycles for the interrupt clear to take effect when the 32 kHz internal oscillator is used.
Ensure that the register write has fully completed before returning from the interrupt handler. Use the data synchronization barrier (DSB)
instruction if necessary. The following is a code example showing how to implement the DSB ARM Cortex-M3 instruction in a C program.
void Ext_Int4_Handler ()
{
EiClr(EXTINT4);
__DSB();
}
During that time, the device must not be placed in any of the power-down modes. IRQCRY (T4STA[6]) indicates when the device can be
placed in power-down mode.
The timer is stopped and reset when clearing the timer enable bit in the T4CON register (T4CON[7]).

REGISTER SUMMARY: WAKE-UP TIMER

Table 253. Wake-Up Timer Register Summary
Address Name
0x40002500 T4VAL0
0x40002504 T4VAL1
0x40002508 T4CON
0x4000250C T4INC
0x40002510 T4WUFB0
0x40002514 T4WUFB1
0x40002518 T4WUFC0
0x4000251C T4WUFC1
0x40002520 T4WUFD0
0x40002524 T4WUFD1
0x40002528 T4IEN
0x4000252C T4STA
0x40002530 T4CLRI
0x4000253C T4WUFA0
0x40002540 T4WUFA1

REGISTER DETAILS: WAKE-UP TIMER

Current Count Value—Least Significant 16 Bits Register
Address: 0x40002500, Reset: 0x0000, Name: T4VAL0
Table 254. Bit Descriptions for T4VAL0
Bits Bit Name
[15:0] T4VALL
Current Count Value—Most Significant 16 Bits Register
Address: 0x40002504, Reset: 0x0000, Name: T4VAL1
Table 255. Bit Descriptions for T4VAL1
Bits Bit Name
[15:0] T4VALH
Description
Current count value—least significant 16 bits
Current count value—most significant 16 bits
Control register
12-bit interval for Wake-Up Field A
Wake-Up Field B—least significant 16 bits
Wake-Up Field B—most significant 16 bits
Wake-Up Field C—least significant 16 bits
Wake-Up Field C—most significant 16 bits
Wake-Up Field D—least significant 16 bits
Wake-Up Field D—most significant 16 bits
Interrupt enable register
Status register
Clear interrupt register
Wake-Up Field A—least significant 16 bits
Wake-Up Field A—most significant 16 bits
Description
Current count low. Least significant 16 bits of current count value.
Description
Current count high. Most significant 16 bits of current count value.
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ADuCM310 Hardware Reference Manual
Reset Access
0x0000 R
0x0000 R
0x0040 RW
0x00C8 RW
0x1FFF RW
0x0000 RW
0x2FFF RW
0x0000 RW
0x3FFF RW
0x0000 RW
0x0000 RW
0x0000 R
0x0000 W
0x1900 R
0x0000 R
Reset Access
0x0 R
Reset Access
0x0 R