ADuCM310 Hardware Reference Manual
REGISTER DETAILS: DIGITAL INPUT/OUTPUT
GPIO Port Configuration Registers
Address: 0x40020000, Reset: 0x0000, Name: GP0CON
Address: 0x40020040, Reset: 0x0000, Name: GP1CON
Address: 0x40020080, Reset: 0x0000, Name: GP2CON
Table 132. Bit Descriptions for GP0CON, GP1CON, and GP2CON
Bits
Bit Name
[15:14]
CON7
[13:12]
CON6
[11:10]
CON5
[9:8]
CON4
[7:6]
CON3
[5:4]
CON2
[3:2]
CON1
[1:0]
CON0
1
Where x is 0 for Port 0, 1 for Port 1, and 2 for Port 2.
2
Reset value for Port 0 and Port 1 is 0x0. Reset value for Port 2 is 0x1.
GPIO Port Output Enable Registers
Address: 0x40020004, Reset: 0x00, Name: GP0OEN
Address: 0x40020044, Reset: 0x00, Name: GP1OEN
Address: 0x40020084, Reset: 0x00, Name: GP2OEN
Table 133. Bit Descriptions for GP0OEN, GP1OEN, and GP2OEN
Bits
Bit Name
[7:0]
OE
GPIO Port Pull-Up Enable Registers
Address: 0x40020008, Reset: 0x00, Name: GP0PUL
Address: 0x40020048, Reset: 0x00, Name: GP1PUL
Address: 0x40020088, Reset: 0x00, Name: GP2PUL
Table 134. Bit Descriptions for GP0PUL, GP1PUL, and GP2PUL
Bits
Bit Name
[7:0]
PUL
GPIO Port Input Path Enable Registers
Address: 0x4002000C, Reset: 0x00, Name: GP0IE
Address: 0x4002004C, Reset: 0x00, Name: GP1IE
Address: 0x4002008C, Reset: 0x00, Name: GP2IE
Table 135. Bit Descriptions for GP0IE, GP1IE, and GP2IE
Bits
Bit Name
[7:0]
IEN
Description
1
Configuration bits for Port x.7. See Table 130.
Configuration bits for Port x.6. See Table 130.
Configuration bits for Port x.5. See Table 130.
Configuration bits for Port x.4. See Table 130.
Configuration bits for Port x.3. See Table 130.
Configuration bits for Port x.2. See Table 130.
Configuration bits for Port x.1. See Table 130.
Configuration bits for Port x.0. See Table 130.
Description
Pin output drive enable.
0: disable the output on the corresponding GPIO.
1: enable the output on the corresponding GPIO.
Description
Pin pull-up enable.
0: disable the pull-up on the corresponding GPIO.
1: enable the pull-up on the corresponding GPIO.
Description
Input path enable. Must be set for external interrupts and to read the pin value.
0: disable the input path on the corresponding GPIO.
1: enable the input path on the corresponding GPIO.
Rev. C | Page 103 of 192
UG-549
Reset
Access
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
2
0xx
RW
0x0
RW
0x0
RW
Reset
Access
0x00
RW
Reset
Access
0x00
RW
Reset
Access
0xFF
RW
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