Analog Devices ADuCM310 Hardware Reference Manual page 41

ADuCM310 Hardware Reference Manual
IDAC1 Data Register
Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT
Table 30. Bit Descriptions for IDAC1DAT
Bits Bit Name
[31:28] RESERVED
[27:17] DATH
[16:12] DATL
[11:6] RESERVED
[5:0] SYNC
IDAC1 Control Register
Address: 0x4008680C, Reset: 0x01, Name: IDAC1CON
Table 31. Bit Descriptions for IDAC1CON
Bits Bit Name
7 CLRB
6 SHT_EN
[5:2] BW
1 PUL
0 PD
IDAC2 Data Register
Address: 0x40086810, Reset: 0x00000000, Name: IDAC2DAT
Table 32. Bit Descriptions for IDAC2DAT
Bits Bit Name
[31:28] RESERVED
[27:17] DATH
[16:12] DATL
[11:6] RESERVED
[5:0] SYNC
Description
Reserved. Write 0.
IDAC1 high data.
IDAC1 low data.
Reserved.
IDAC1 synchronization bits. These six bits are common to the six IDACs.
Each bit set to 1 prevents the corresponding channel from updating
immediately. The channel updates when the bit changes to 0.
Description
IDAC1 clear bit.
0: clear IDAC1DAT.
1: enable write.
IDAC1 shutdown enable. Enables automatic shutdown in case of
overtemperature.
0: disable this function.
1: enable this function.
IDAC1 bandwidth. See the IDAC Output Filter section for more details.
IDAC1 pull down.
0: disable the pull-down current source.
1: enable the pull-down current source.
IDAC1 power down.
0: powers up IDAC1.
1: powers down IDAC1.
Description
Reserved. Write 0.
IDAC2 high data.
IDAC2 low data.
Reserved.
IDAC2 synchronization bits. These six bits are common to the six IDACs.
Each bit set to 1 prevents the corresponding channel from updating
immediately. The channel updates when the bit changes to 0.
Rev. C | Page 41 of 192
UG-549
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 R
0x00 RW
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x1 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 R
0x00 RW