Analog Devices ADuCM310 Hardware Reference Manual page 145

ADuCM310 Hardware Reference Manual
Bits Bit Name
5 TX
4 TXUR
[3:1] TXFSTA
0 IRQ
Receive Register
Address: 0x40030004, Reset: 0x0000, Name: SPI1RX
Table 207. Bit Descriptions for SPI1RX
Bits Bit Name
[15:8] DMA_DATA_BYTE_2
[7:0] DATA_BYTE_1
Transmit Register
Address: 0x40030008, Reset: 0x0000, Name: SPI1TX
Table 208. Bit Descriptions for SPI1TX
Bits Bit Name
[15:8] DMA_DATA_BYTE_2
[7:0] DATA_BYTE_1
Baud Rate Selection Register
Address: 0x4003000C, Reset: 0x0000, Name: SPI1DIV
Table 209. Bit Descriptions for SPI1DIV
Bits Bit Name
[15:9] RESERVED
8 CSIRQ_EN
7 BCRST
Description
SPI Tx IRQ. Status bit. Not available in DMA mode.
0: CLR. Cleared to 0 when the SPI1STA register is read.
1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in
SPI1CON is set and the required number of bytes have been transmitted.
SPI Tx FIFO underflow.
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when a transmit is initiated without any valid data in the Tx FIFO.
This bit generates an interrupt, except when TFLUSH is set in SPI1CON.
SPI Tx FIFO status.
000: Tx FIFO empty.
001: 1 valid byte in FIFO.
010: 2 valid bytes in FIFO.
011: 3 valid bytes in FIFO.
100: 4 valid bytes in FIFO.
SPI interrupt status.
0: cleared to 0 after reading SPI1STA.
1: set to 1 when an SPI based interrupt occurs.
Description
8-bit receive buffer. These 8 bits are used only in the DMA mode, where all
FIFO accesses happen as half-word access. They return 0s if DMA is disabled.
8-bit receive buffer.
Description
8-bit transmit buffer. These 8 bits are used only in the DMA mode, where all
FIFO accesses happen as half-word access. They return 0s if DMA is disabled.
8-bit transmit buffer.
Description
Reserved.
Enable interrupt on every CS edge in continuous mode. If this bit is set and the
SPI module is in continuous mode, any edge on CS generates an interrupt and
the corresponding status bits (CSRSG, CSFLG) are asserted. If this bit is clear, no
interrupt is generated. This bit has no effect if the SPI is not in continuous mode
and high speed mode.
Reset mode for CSERR. If this bit is set, the bit counter is reset after a CS error
condition and the Cortex is expected to clear the SPI enable bit. If this bit is clear,
the bit counter continues from where it stopped. SPI can receive the remaining
bits when CS is asserted, and Cortex must ignore the CSERR interrupt. However,
it is strongly recommended to set this bit for a graceful recovery after a CS error.
Rev. C | Page 145 of 192
UG-549
Reset Access
0x0 RC
0x0 RC
0x0 R
0x0 RC
Reset Access
0x0 R
0x0 R
Reset Access
0x0 W
0x0 W
Reset Access
0x0 R
0x0 RW
0x0 RW