Analog Devices ADuCM310 Hardware Reference Manual page 12

UG-549
User Clock Gating Control Register
Address: 0x40028014, Reset: 0x0040, Name: CLKCON5
The user clock gating control register (CLKCON5) controls the gates of the peripheral UCLKs.
Table 7. Bit Descriptions for CLKCON5
Bits Bit Name
[15:7] RESERVED
6 RESERVED
5 UCLKUARTOFF
4 UCLKI2C1OFF
3 UCLKI2C0OFF
2 RESERVED
1 UCLKSPI1OFF
0 UCLKSPI0OFF
Description
Reserved. Always returns 0 when read.
Reserved. Always set to 1.
UART clock user control. This bit disables the UCLK UART clock. It controls the
gate on UCLK UART in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK_UART is always off and this bit has no effect.
0: die-to-die clock on permanently.
1: die-to-die clock enabled only during die-to-die transfers (recommended).
2
I C1 clock user control. This bit disables the UCLK I
2
gate on UCLK I C1 in Power Mode 0 and Power Mode 1. In Power Mode 2
2
and Power Mode 3, the I C1 UCLK is always off and this bit has no effect.
0: clock on.
1: clock off.
2
I C0 clock user control. This bit disables the UCLK I
2
gate on UCLK I C0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK I
0: clock on.
1: clock off.
Reserved.
SPI1 clock user control. This bit disables the UCLK SPI1 clock. It controls the
gate on UCLK SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK SPI1 is always off and this bit has no effect.
0: clock on.
1: clock off.
SPI0 clock user control. This bit disables the UCLK SPI0 clock. It controls the
gate on UCLK SPI0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK SPI0 is always off and this bit has no effect.
0: clock on.
1: clock off.
Rev. C | Page 12 of 192
ADuCM310 Hardware Reference Manual
2
C1 clock. It controls the
2
C0 clock. It controls the
2 C0 is always off and this bit has no effect.
Reset Access
0x0 R
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 R
0x0 RW
0x0 RW