Register Summary: I 2 C0 - Analog Devices ADuCM310 Hardware Reference Manual

UG-549
If the address byte is 0x01, a hardware general call is issued. Byte 2 in this case is the hardware master address.
The general call interrupt status bit is set on any general call after the second byte is received, and user code must take corrective action to
reprogram the device address.
If GCEN is asserted, the slave always acknowledges the first byte of a general call. It acknowledges the second byte of a general call if the
second byte is 0x04 or 0x06, or if the second byte is a hardware general call, and HGCEN (I2CxSCON[3]) is asserted.
The I2CxALT register contains the alternate device ID for a hardware general call sequence. If the hardware general call enable bit,
HGCEN, GCEN, and SLVEN are all set, the device recognizes a hardware general call. When a general call sequence is issued and the
second byte of the sequence is identical to ALT, the hardware call sequence is recognized for the device.
I 2 C Reset Mode
The slave state machine is reset when SLVEN is written to 0.
The master state machine is reset when MASEN is written to 0.
2
I C Test Modes
The device can be placed in an internal loopback mode by setting the LOOPBACK bit (I2CxMCON[2]). There are four FIFOs (master Tx
and Rx, and slave Tx and Rx); therefore, in effect, the I
the master is set up to address the slave address.
2
I C Low Power Mode
If the master and slave are both disabled (MASEN = SLVEN = 0), the I
clock to the I 2 C section of the chip by setting CLKCON5[4:3] = 0x3.
DMA Requests
Four DMA channels are required to service the I
master control register.
REGISTER SUMMARY: I
2
Table 152. I C0 Register Summary
Address Name
0x40003000 I2CMCON
0x40003004 I2CMSTA
0x40003008 I2CMRX
0x4000300C I2CMTX
0x40003010 I2CMRXCNT
0x40003014 I2CMCRXCNT
0x40003018 I2CADR0
0x4000301C I2CADR1
0x40003024 I2CDIV
0x40003028 I2CSCON
0x4000302C I2CSSTA
0x40003030 I2CSRX
0x40003034 I2CSTX
0x40003038 I2CALT
0x4000303C I2CID0
0x40003040 I2CID1
0x40003044 I2CID2
0x40003048 I2CID3
0x4000304C I2CFSTA
0x40003050 I2C0SHCON
0x40003058 I2CASSCL
2 C peripheral can be set up to talk to itself. External loopback can be performed if
2
C master and slave. DMA enable bits are provided in the slave control register and in the
2
C0
Description
Master control register
Master status register
Master receive data register
Master transmit data register
Master receive data count register
Master current receive data count register
First master address byte register
Second master address byte register
Serial clock period divisor register
Slave control register
2
Slave I C status/error/IRQ register
Slave receive register
Slave transmit register
Hardware general call ID register
First slave address device ID register
Second slave address device ID register
Third slave address device ID register
Fourth slave address device ID register
Master and slave FIFO status register
Master and slave shared control register
Automatic stretch control register for master and slave mode
ADuCM310 Hardware Reference Manual
2
C section is off. To fully power down the I
Rev. C | Page 114 of 192
2
C block, disable the
Reset Access
0x0000 RW
0x6000 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 R
0x0000 RW
0x0000 RW
0x1F1F RW
0x0000 RW
0x0001 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 W
0x0000 RW