Analog Devices ADuCM310 Hardware Reference Manual page 11

ADuCM310 Hardware Reference Manual
Bits Bit Name
[10:8] RESERVED
[7:4] CLKOUT
[3:2] RESERVED
[1:0] CLKMUX
Clock Dividers Register
Address: 0x40028004, Reset: 0x0200, Name: CLKCON1
Table 6. Bit Descriptions for CLKCON1
Bits Bit Name
[15:11] RESERVED
[10:8] CDPCLK
[7:3] RESERVED
[2:0] CDHCLK
Description
Reserved.
GPIO clock out selection.
0000: UCLK.
0001: LFOSC (32 kHz).
0010: HFOSC (16 MHz).
0100: core clock (default).
0101: PCLK.
1011: General-Purpose Timer 0 clock.
1100: wake-up timer clock.
1110: HFXTAL.
All other combinations are reserved.
Reserved.
Clock selection.
00: high frequency internal oscillator (HFOSC).
01: SPLL is selected (80 MHz).
10: UPLL is selected (60 MHz).
11: external GPIO port is selected (ECLKIN).
Description
Reserved
PCLK divide bits.
000: Reserved.
001: Reserved.
010: DIV4. Divide by 4 (PCLK is a quarter the frequency of root clock, 20 MHz).
All ADC specifications are based on this setting. Using any other setting may
affect ADC performance.
011: DIV8. Divide by 8.
100: DIV16. Divide by 16.
101: DIV32. Divide by 32.
110: DIV64. Divide by 64.
111: DIV128. Divide by 128.
Reserved. Always returns 0 when read.
HCLK divide bits.
000: DIV1. Divide by 1 (HCLK is equal to root clock).
001: DIV2. Divide by 2 (HCLK is half the frequency of root clock).
010: DIV4. Divide by 4 (HCLK is quarter the frequency of root clock).
011: DIV8. Divide by 8.
100: DIV16. Divide by 16.
101: DIV32. Divide by 32.
110: DIV64. Divide by 64.
111: DIV128. Divide by 128.
Rev. C | Page 11 of 192
UG-549
Reset Access
0x0 RW
0x4 RW
0x0 R
0x1 RW
Reset Access
0x0 R
0x2 RW
0x0 R
0x0 RW