Clocking Architecture; Clocking Architecture Features; Clocking Architecture Block Diagram - Analog Devices ADuCM310 Hardware Reference Manual

ADuCM310 Hardware Reference Manual

CLOCKING ARCHITECTURE

CLOCKING ARCHITECTURE FEATURES

The ADuCM310 integrates two on-chip oscillators and circuitry for an external crystal and external clock source:
•
LFOSC is a 32 kHz, low power internal oscillator that is used in low power modes.
•
HFOSC is a 16 MHz internal oscillator that is used in active mode. This is the default input to the PLL.
•
HFXTAL is a 16 MHz external crystal oscillator.
•
External clock input (ECLKIN) is available via the GPIO pin.

CLOCKING ARCHITECTURE BLOCK DIAGRAM

HFXTAL
16MHz OSC
HFOSC
16MHz OSC
ECLKIN
P1.0
LFOSC
(INTERNAL)
PCLK
PCLK
HCLK
PCLK
HCLK
PCLK
HCLK
0
80MHz SPLL
1
CLKCON0[11]
01
UCLK
00
11
CLKCON0[1:0]
WATCHDOG
TIMER
01
11 WAKE-UP
TIMER
00
T4CON[9:10]
00
01
TIMER0CLK
11
10
T0CON[5:6]
00
01
11
TIMER1CLK
10
T1CON[5:6]
00
01
TIMER2CLK
11
10
T2CON[5:6]
Figure 3. Clocking Architecture Block Diagram
Rev. C | Page 9 of 192
÷4
CLKCON5[3]
CLKCON5[4]
CDPCLK
(CLKCON1[10:8])
CLKCON5[5]
CLKCON5[6]
CDD2DCLK
(CLKCON1[11])
CLKCON5[0]
CLKCON5[1]
HCLK
CDHCLK
(CLKCON1[2:0])
UG-549
ACLK
(TO LV DIE, ADC)
2
I C0
2
I C1
UART
PCLK
D2D
SPI0
SPI1
CORE
PWM
FLASH