Register Details: I 2 C1 - Analog Devices ADuCM310 Hardware Reference Manual

ADuCM310 Hardware Reference Manual
2
REGISTER DETAILS: I C1
Master Control Register
Address: 0x40003400, Reset: 0x0000, Name: I2C1MCON
Table 175. Bit Descriptions for I2C1MCON
Bits Bit Name
[15:12] RESERVED
11 MTXDMA
10 MRXDMA
9 RESERVED
8 IENCMP
7 IENACK
6 IENALOST
5 IENMTX
4 IENMRX
3 STRETCH
2 LOOPBACK
1 COMPETE
0 MASEN
Description
Reserved.
Enable master Tx DMA request.
0: disable DMA mode.
2
1: enable I C master DMA Tx requests.
Enable master Rx DMA request.
0: disable DMA mode.
1: enable I 2 C master DMA Rx requests.
Reserved.
Transaction completed (or stop detected) interrupt enable.
0: an interrupt is not generated when a stop is detected.
1: an interrupt is generated when a stop is detected.
Acknowledge not received interrupt enable.
0: disable acknowledge not received interrupt.
1: enable acknowledge not received interrupt.
Arbitration lost interrupt enable.
0: disable arbitration lost interrupt.
1: enable arbitration lost interrupt.
Transmit request interrupt enable.
0: disable transmit request interrupt.
1: enable transmit request interrupt.
Receive request interrupt enable.
0: disable receive request interrupt.
1: enable receive request interrupt.
Stretch SCL enable.
0: disable Clock stretching.
1: setting this bit tells the device if SCL is 0, hold it at 0; or if SCL is 1, when
it next goes to 0, hold it at 0.
Internal loopback enable. Note that is also possible for the master to loop
back a transfer to the slave as long as the device address corresponds, that
is, external loopback.
0: SCL and SDA out of the device are not muxed onto their corresponding
inputs.
1: SCL and SDA out of the device are muxed onto their corresponding
inputs.
Start backoff disable. Setting this bit enables the device to compete for
ownership even if another device is currently driving a start condition.
Master enable. Disable the master when not in use to gate the clock to the
master and save power. Do not clear this bit until a transaction has completed;
see the TCOMP bit in the master status register.
0: master is disabled.
1: master is enabled.
Rev. C | Page 125 of 192
UG-549
Reset Access
0x0 R
0x0 W
0x0 W
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW