Register Summary: Power Management Unit; Register Details: Power Management Unit - Analog Devices ADuCM310 Hardware Reference Manual

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REGISTER SUMMARY: POWER MANAGEMENT UNIT

Table 9. Power Management Register Summary
Address Name
0x40002400 PWRMOD
0x40002404 PWRKEY

REGISTER DETAILS: POWER MANAGEMENT UNIT

Power Modes Register
Address: 0x40002400, Reset: 0x0000, Name: PWRMOD
Table 10. Bit Descriptions for PWRMOD
Bits Bit Name
[14:2] RESERVED
[1:0] PWRMOD
Key Protection for PWRMOD Register
Address: 0x40002404, Reset: 0x0000, Name: PWRKEY
Table 11. Bit Descriptions for PWRKEY
Bits Bit Name
[15:0] PWRKEY
Description
Power modes
Key protection for PWRMOD
Description
Reserved. These bits must be written 0 by user code.
Power modes control bits. When read, these bits contain the last power
mode value entered by user code. Note that, to place the Cortex in
SLEEPDEEP mode for hibernate, the Cortex-M3 system control register
(Register 0xE000ED10) must be configured to 0x4 or 0x06.
00: active mode.
01: CORE_SLEEP mode.
10: SYS_SLEEP mode.
11: hibernate mode.
Description
Power control key register. The PWRMOD register is key-protected. Two
writes to the key are necessary to change the value in the PWRMOD register:
first 0x4859, then 0xF27B. The PWRMOD register must then be written. A
write to any other register before writing to PWRMOD returns the protection
to the lock state.
Rev. C | Page 16 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x0000 RW
0x0000 RW
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 RW