Analog Devices ADuCM310 Hardware Reference Manual page 51

ADuCM310 Hardware Reference Manual
DAC3 Control Register
Address: 0x4008240C, Reset: 0x0100, Name: DAC3CON
Table 49. Bit Descriptions for DAC3CON
Bits Bit Name
[15:9] RESERVED
8 DAC3_PD
[7:5] RESERVED
4 DAC3_EN
[3:2] RESERVED
[1:0] DAC3_RN
DAC4 Control Register
Address: 0x40082410, Reset: 0x0100, Name: DAC4CON
Table 50. Bit Descriptions for DAC4CON
Bits Bit Name
[15:11] RESERVED
10 DAC4_DRV
9 DAC4_10N
8 DAC4_PD
[7:5] RESERVED
4 DAC4_EN
[3:2] RESERVED
[1:0] DAC4_RN
Description
Reserved.
DAC3 power down.
0: DAC3 is powered up.
1: DAC3 is powered down and output is floating.
Reserved.
DAC3 enable. Must be set to 1.
0: DAC disable. Clear DAC data immediately.
1: DAC enable.
Reserved.
DAC3 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference.
01: reserved.
10: reserved.
11: AV /AGND.
DD
Description
Reserved.
DAC4 increased drive.
0: normal drive.
1: for 300 Ω load.
DAC4 high load.
0: normal load.
1: can drive 10 nF and full scale = 3 V.
DAC4 power down.
0: DAC4 is powered up.
1: DAC4 is powered down and output is floating.
Reserved.
DAC4 enable. Must be set to 1.
0: DAC disable. Clear DAC data immediately.
1: DAC enable.
Reserved.
DAC4 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference.
01: reserved.
10: reserved.
11: AV /AGND.
DD
Rev. C | Page 51 of 192
UG-549
Reset Access
0x0 R
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW