Analog Devices ADuCM310 Hardware Reference Manual page 154

UG-549
Bits Bit Name
5 SP
4 EPS
3 PEN
2 STOP
[1:0] WLS
Modem Control Register
Address: 0x40005010, Reset: 0x0000, Name: COMMCR
Table 219. Bit Descriptions for COMMCR
Bits Bit Name
[15:5] RESERVED
4 LOOPBACK
3 OUT2
2 OUT1
1 RTS
0 DTR
Description
Stick parity. Forces parity to defined values. When set, the parity is based
on the following bit settings:
EPS = 1 and PEN = 1, parity is forced to 0.
EPS = 0 and PEN = 1, parity is forced to 1.
EPS = X and PEN = 0, no parity is transmitted.
0: parity is not forced based on EPS and PEN.
1: parity forced based on EPS and PEN.
Parity select. This bit only has meaning if parity is enabled (PEN set).
0: odd parity is transmitted and checked.
1: even parity is transmitted and checked.
Parity enable. Controls the parity bit transmitted and checked. The value
transmitted and the value checked are based on the settings of EPS and SP.
0: parity is not transmitted or checked.
1: parity is transmitted and checked.
Stop bit. Controls the number of stop bits transmitted. In all cases, only the
first stop bit is evaluated on data received.
0: send 1 stop bit regardless of the word length (WLS).
1: send a number of stop bits based on the word length. Transmit 1.5 stop
bits if the word length is 5 bits (WLS = 00), or 2 stop bits if the word length
is 6 (WLS = 01), 7 (WLS = 10), or 8 bits (WLS = 11).
Word length select. Selects the number of bits per transmission.
00: 5 bits.
01: 6 bits.
10: 7 bits.
11: 8 bits.
Description
Reserved.
Loopback mode. In loopback mode, SOUT is forced high. The modem
signals are also directly connected to the status inputs (RTS to CTS, DTR to
DSR, OUT1 to RI, and OUT2 to DCD).
0: normal operation; loopback disabled.
1: loopback enabled.
Output 2.
0: force OUT2 to a Logic 1.
1: force OUT2 to a Logic 0.
Output 1.
0: force OUT1 to a Logic 1.
1: force OUT1 to a Logic 0.
Request to send.
0: force RTS to a Logic 1.
1: force RTS to a Logic 0.
Data terminal ready.
0: force DTR to a Logic 1.
1: force DTR to a Logic 0.
Rev. C | Page 154 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW