Analog Devices ADuCM310 Hardware Reference Manual page 175

ADuCM310 Hardware Reference Manual
Control Register
Address: 0x40002508, Reset: 0x0040, Name: T4CON
Table 256. Bit Descriptions for T4CON
Bits Bit Name
[15:12] RESERVED
11 STOP_WUFA
[10:9] CLK
8 WUEN
7 ENABLE
6 MOD
[5:4] RESERVED
3 FREEZE
2 RESERVED
[1:0] PRE
12-Bit Interval for Wake-Up Field A Register
Address: 0x4000250C, Reset: 0x00C8, Name: T4INC
Table 257. Bit Descriptions for T4INC
Bits Bit Name
[15:12] RESERVED
[11:0] INTERVAL
Wake-Up Field B—Least Significant 16 Bits Register
Address: 0x40002510, Reset: 0x1FFF, Name: T4WUFB0
Table 258. Bit Descriptions for T4WUFB0
Bits Bit Name
[15:0] T4WUFBL
Description
Reserved.
Disables updating Field A register T4WUFA. When set, this bit stops the
Wake-Up Field A register T4WUFA from being updated with the interval
register I2INC value. This allows the user to update the interval T4INC or
T4WUFA registers safely.
Clock select.
00: PCLK: peripheral clock (default).
01: LFOSC: 32 kHz internal oscillator.
10: LFOSC: 32kHz internal oscillator.
11: ECLKIN: external clock from P1.0.
Wake-up enable.
0: DIS: Cleared by user to disable the wake-up timer when the core clock is off.
1: EN: Set by user to enable the wake-up timer even when the core clock is off.
Timer enable.
0: DIS: Disable the timer (default).
1: EN: Enable the timer.
Timer mode.
0: PERIODIC: Cleared by user to operate in periodic mode. In this mode, the
timer counts up to T4WUFD.
1: FREERUN: Set by user to operate in free running mode (default).
Reserved. Write these bits 0.
Freeze enable.
0: DIS: Cleared by user to disable this feature (default).
1: EN: Set by user to enable the freeze of the high 16 bits after the lower
bits have been read from T4VAL0. This ensures that the software reads an
atomic shot of the timer. T4VAL1 unfreezes after it has been read.
Reserved.
Prescaler.
00: PREDIV1: Source Clock/1 (default). If the selected clock source is PCLK,
this setting results in a prescaler of 4.
01: PREDIV16: Source Clock/16.
10: PREDIV256: Source Clock/256.
11: PREDIV32768: Source Clock/32,768.
Description
Reserved
Interval for Wake-Up Field A
Description
Wake-Up Field B low. Least significant 16 bits of Wake-Up Field B.
Rev. C | Page 175 of 192
UG-549
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0C8 RW
Reset Access
0x1FFF RW