Analog Devices ADuCM310 Hardware Reference Manual page 76

UG-549
DMA Channel Enable Clear Register
Address: 0x4001002C, Reset: 0x00000000, Name: DMAENCLR
Table 95. Bit Descriptions for DMAENCLR
Bits Bit Name
[31:14] RESERVED
[13:0] CHENCLR
DMA Channel Primary-Alternate Set Register
Address: 0x40010030, Reset: 0x00000000, Name: DMAALTSET
The DMAALTSET register enables the user to configure the appropriate DMA channel to use the alternate control data structure.
Reading the register returns the status of which data structure is in use for the corresponding DMA channel. Each bit of the register
represents the corresponding channel number in the DMA controller.
Note that the DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather, and peripheral
scatter-gather transfers.
Table 96. Bit Descriptions for DMAALTSET
Bits Bit Name
[31:14] RESERVED
[13:0] CHPRIALTSET
DMA Channel Primary-Alternate Clear Register
Address: 0x40010034, Reset: 0x00000000, Name: DMAALTCLR
The DMAALTCLR write-only register enables the user to configure the appropriate DMA channel to use the primary control data
structure. Each bit of the register represents the corresponding channel number in the DMA controller.
Note that the DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather, and peripheral
scatter-gather transfers.
Table 97. Bit Descriptions for DMAALTCLR
Bits Bit Name Description
[31:14] RESERVED Reserved. Undefined.
[13:0] CHPRIALTCLR Select primary data structure. Set the appropriate bit to select the primary data structure for
the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and Bit M − 1
corresponds to DMA Channel M − 1.
When written:
Bit C = 0: no effect. Use the DMAALTSET register to select the alternate data structure.
Bit C = 1: selects the primary data structure for Channel C.
Description
Reserved. Undefined.
Disable DMA channels. This register allows the disabling of DMA channels.
Reading the register returns the enable status of the channels. Each bit of
the register represents the corresponding channel number in the DMA
controller. (Note that the controller disables a channel automatically, by
setting the appropriate bit, when it completes the DMA cycle.) Set the
appropriate bit to disable the corresponding channel. Bit 0 corresponds to
DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1.
When written:
Bit C = 0: no effect. Use the DMAENSET register to enable the channel.
Bit C = 1: disables Channel C.
Description
Reserved. Undefined.
Control structure status/select alternate structure. Returns the channel
control data structure status, or selects the alternate data structure for the
corresponding DMA channel. Bit 0 corresponds to DMA Channel 0, and
Bit M − 1 corresponds to DMA Channel M − 1.
When read:
Bit C = 0: DMA Channel C is using the primary data structure.
Bit C = 1: DMA Channel C is using the alternate data structure.
When written:
Bit C = 0: no effect. Use the DMAALTCLR register to set Bit C to 0.
Bit C = 1: selects the alternate data structure for Channel C.
Rev. C | Page 76 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x0 R
0x0 W
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 W