UG-549
GPIO Port 3 Configuration Register
Address: 0x400200C0, Reset: 0x0000, Name: GP3CON
Table 142. Bit Descriptions for GP3CON
Bits
Bit Name
[15:10]
RESERVED
[9:8]
CON4
[7:6]
RESERVED
[5:4]
CON2
[3:2]
CON1
[1:0]
CON0
GPIO Port 3 Output Enable Register
Address: 0x400200C4, Reset: 0x00, Name: GP3OEN
Table 143. Bit Descriptions for GP3OEN
Bits
Bit Name
[7:5]
RESERVED
4
OEN
3
RESERVED
2
OEN
1
OEN
0
OEN
GPIO Port 3 Pull-Up Enable Register
Address: 0x400200C8, Reset: 0x00, Name: GP3PUL
Table 144. Bit Descriptions for GP3PUL
Bits
Bit Name
[7:5]
RESERVED
4
PUL
3
RESERVED
2
PUL
1
PUL
0
PUL
Description
Reserved.
Configuration bits for Port 3.4. See Table 130.
Reserved.
Configuration bits for Port 3.2. See Table 130.
Configuration bits for Port 3.1. See Table 130.
Configuration bits for Port 3.0. See Table 130.
Description
Reserved.
Pin output drive enable.
0: disable the output on P3.4.
1: enable the output on P3.4.
Reserved.
Pin output drive enable.
0: disable the output on P3.2.
1: enable the output on P3.2.
Pin output drive enable.
0: disable the output on P3.1.
1: enable the output on P3.1.
Pin output drive enable.
0: disable the output on P3.0.
1: enable the output on P3.0.
Description
Reserved.
Pin pull-up enable.
0: disable the pull-up on P3.4.
1: enable the pull-up on P3.4.
Reserved.
Pin pull-up enable.
0: disable the pull-up on P3.2.
1: enable the pull-up on P3.2.
Pin pull-up enable.
0: disable the pull-up on P3.1.
1: enable the pull-up on P3.1.
Pin pull-up enable.
0: disable the pull-up on P3.0.
1: enable the pull-up on P3.0.
Rev. C | Page 106 of 192
ADuCM310 Hardware Reference Manual
Reset
Access
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Reset
Access
0x00
R
0x0
RW
0x0
R
0x0
RW
0x0
RW
0x0
RW
Reset
Access
0x00
R
0x0
RW
0x0
R
0x0
RW
0x0
RW
0x0
RW
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