Analog Devices ADuCM310 Hardware Reference Manual page 119

ADuCM310 Hardware Reference Manual
Slave Control Register
Address: 0x40003028, Reset: 0x0000, Name: I2CSCON
Table 162. Bit Descriptions for I2CSCON
Bits Bit Name
15 RESERVED
14 STXDMA
13 SRXDMA
12 IENREPST
11 SXMITDEC
10 IENSTX
9 IENSRX
8 IENSTOP
7 NACK
6 STRETCHSCL
5 EARLYTXR
4 GCSBCLR
3 HGCEN
2 GCEN
1 ADR10EN
0 SLVEN
Description
Reserved.
Enable slave Tx DMA request. Set to 1 by user code to enable I
Rx requests. Cleared by user code to disable DMA mode.
Enable slave Rx DMA request. Set to 1 by user code to enable I
DMA Rx requests. Cleared by user code to disable DMA mode.
Repeated start interrupt enable. If 1, an interrupt is generated when the
REPSTART status bit asserts. If 0, an interrupt is not generated when the
REPSTART status bit asserts.
Decrement slave Tx FIFO status when a byte has been transmitted. If set to 1,
the transmit FIFO status is decremented when a byte has been transmitted.
If set to 0, the transmit FIFO status is decremented when the byte is unloaded
from the FIFO into a shadow register at the start of byte transmission.
Slave transmit request interrupt enable.
Slave receive request interrupt enable.
Stop condition detected interrupt enable.
No acknowledge next communication. If this bit is set, the next
communication is not acknowledged. This can be used, for example, if
during a 24xx style access, an attempt was made to write to a read only or
nonexistent location in system memory. That is the indirect address in a
24xx style write pointed to an unwritable memory location.
Stretch SCL enable. Setting this bit tells the device, if SCL is 0, hold it at 0;
or, if SCL is 1, hold it at 0 when it next goes to 0.
Early transmit request mode. Setting this bit enables a transmit request
just after the positive edge of the direction bit SCL clock pulse.
General call status bit clear. The general call status and general call ID bits are
cleared when a 1 is written to this bit. The general call status and general call ID
bits are not reset by anything other than a write to this bit or a full reset.
Hardware general call enable. When this bit and the general call enable bit
are set, the device after receiving a general call, Address 00h, and a data byte,
checks the contents of the ALT against the receive shift register. If they match,
the device has received a hardware general call. When a device requires
urgent attention from a master device without knowing which master it
requires to turn to, it can use this call. This is a call "to whom it may concern. "
The device that requires attention embeds its own address into the message.
The LSB of the ALT register must always be written to a 1, as per I
January 2000 specification.
General call enable. This bit enables the I
general call, Address 0x00 (write).
Enabled 10-bit addressing. If this bit is clear, the slave can support four
slave addresses, programmed in Register I2CID0 to Register I2CID3. When
this bit is set, 10-bit addressing is enabled. One 10-bit address is supported
by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the
first byte of the address and the upper five bits must be programmed to
11110. I2CID3 and I2CID4 can be programmed with 7-bit addresses at the
same time.
Slave enable. When 1, the slave is enabled. When 0, all slave state machine
flops are held in reset, and the slave is disabled. Note that APB writable
register bits are not reset.
Rev. C | Page 119 of 192
2
C slave DMA
2
C slave
2
C
2 C slave to acknowledge an I
UG-549
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 W
0x0 RW
2 C 0x0 RW
0x0 RW
0x0 RW