Serial Peripheral Interface (Spi) 1/2; Table 49. Spi_Sm_0; Table 50. Spi_Sm_1; Table 51. Spi_Sm_2 - ST STM32F2 Series User Manual

3.6.10

Serial peripheral interface (SPI) 1/2

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations None
SM CODE
Description
Ownership
UM1845 - Rev 4
Table 49.
SPI_SM_0
Periodical read-back of configuration registers
End user
This method must be applied to SPI configuration registers.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 50.
SPI_SM_1
Protocol error signals
ST
SPI communication module embeds protocol error checks (like overrun, underrun, timeout etc.)
conceived to detect network-related abnormal conditions. These mechanisms are able anyway to
detect a marginal percentage of hardware random failures affecting the module itself
Error flag raise and optional Interrupt Event generation
Depends on peripheral configuration (e.g. baud rate), refer to functional documentation
Permanent and Transient
None
Depends on implementation
Continuous
NA
SPI_SM_2: Information redundancy techniques on messages
Table 51.
SPI_SM_2
Information redundancy techniques on messages
End user
Description of hardware and software diagnostics
SPI_SM_0
SPI_SM_1
SPI_SM_2
UM1845
Section 3.6.5
page 39/108