ST STM32F2 Series User Manual page 80

STM32F2 Series function
System or peripheral control
Ethernet (ETH): media access control (MAC)
with DMA controller
Flexible static memory controller (FSMC)
SAI
RNG
AES
HASH
DCMI
Part separation (no interference)
® ®
Arm Cortex -M3 CPU
Debug
® ®
Arm Cortex -M3 / Supply system
STM32F2 Series peripherals
Flash subsystem
UM1845 - Rev 4
Diagnostic Description
LOCK_SM_0 Lock mechanism for configuration options
SYSCFG_SM_0 Periodical read-back of configuration registers
Periodical read-back of hardware diagnostics
DIAG_SM_0
configuration registers
Periodical read-back of Ethernet configuration
ETH_SM_0
registers.
ETH_SM_1 Protocol error signals including hardware CRC
Information redundancy techniques on messages,
ETH_SM_2
including end to end safing
FSMC_SM_0 Control flow monitoring in application software
Information redundancy on external memory
FSMC_SM_1
connected to FSMC
Periodical read-back of FSMC configuration
FSMC_SM_2
registers.
FSMC_SM_3 ECC engine on NAND interface in FSMC module
SAI_SM_0 Periodical read-back of SAI configuration registers
SAI_SM_1 SAI output loopback scheme
SAI_SM_2 1oo2 scheme for SAI module
Periodical read-back of RNG configuration register
RNG_SM_0
RNG_CR.
RNG_SM_1 RNG module entropy on-line tests
AES_SM_0 Periodical read-back of AES configuration registers
AES_SM_1 Encryption/decryption collateral detection
Information redundancy techniques on messages,
AES_SM_2
including end-to-end safing
Periodical read-back of HASH configuration
HASH_SM_0
registers
HASH_SM_1 HASH processing collateral detection
Periodical read-back of DCMI configuration
DCMI_SM_0
registers
DCMI_SM_1 DCMI video input data synchronization
FFI_SM_0 Unused peripherals disable
Periodical read-back of interference avoidance
FFI_SM_1
registers
The reset condition of Arm
CoU_1
must be compatible as valid safe state at system
level
STM32F2 Series debug features must not be used
CoU_2
in safety function(s) implementation
Low power mode state must not be used in safety
CoU_3
function(s) implementation
End user must implement the required combination
of safety mechanism/CoUs for each STM32
CoU_4
peripherals used in safety function(s)
implementation
During Flash bank mass erase and reprogramming
CoU_5 there must not be safety functions(s) executed by
STM32F2 MCU.
Conditions of use
Rank Perm Trans
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® ®
Cortex -M3 CPU
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UM1845
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