Table 100. Fsmc_Sm_2; Table 101. Fsmc_Sm_3 - ST STM32F2 Series User Manual

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known
limitations
UM1845 - Rev 4
Table 100. FSMC_SM_2
FSMC_SM_2
Periodical read-back of FSMC configuration registers
End user
This method must be applied to FSMC configuration registers.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
FSMC interface is available only on selected part numbers
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 101. FSMC_SM_3
FSMC_SM_3
ECC engine on NAND interface in FSMC module
ST
The FMC NAND Card controller includes two error correction code computation hardware blocks,
one per memory bank. They reduce the host CPU workload when processing the ECC by software.
ECC mechanism protects data integrity on the external memory connected to NAND port
Refer to functional documentation
ECC bits are checked during a memory reading
Permanent and Transient
FSMC interface is available only on selected part numbers
None
Continuous
Not needed
FSMC_SM_2: Periodical read-back of FSMC configuration registers
This method has negligible efficiency in detecting hardware random failures affecting the FSMC
interface. It can be part of End user safety concept because addressing memories outside
STM32F2 Series MCU
Description of hardware and software diagnostics
UM1845
Section 3.6.5
page 68/108