Table 88. Clk_Sm_3 - ST STM32F2 Series User Manual

SM CODE
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
UM1845 - Rev 4
CLK_SM_2
ST
The independent watchdog IWDG is able to detect failures in internal main MCU clock (lower
frequency)
Reset signal generation
Depends on implementation (watchdog timeout interval)
Permanent
None
IWDG activation. It is recommended to use the "Hardware watchdog" in Option byte settings (IWDG
is automatically enabled after reset)
Continuous
Not needed
CPU_SM_1: control flow monitoring in application software
In case of usage of IWDG window option, end user must consider possible tolerance in application
software execution, to avoid false error reports (affecting system availability)
Table 88. CLK_SM_3
CLK_SM_3
Internal clock cross-measure
End user
This method is implemented using TIM14 capabilities to be fed by the 32 KHz RTC clock or an
external clock source (if available). TIM14 counter progresses are compared with another counter
(fed by internal clock). Abnormal values of oscillator frequency can be therefore detected.
Depends on implementation
Depends on implementation
Permanent
None
Depends on implementation
Periodic
Not needed
CPU_SM_1: control flow monitoring in application software
CPU_SM_5: external watchdog
Efficiency versus transient faults is negligible. It provides only medium efficiency in permanent
clock-related failure mode coverage
Description of hardware and software diagnostics
UM1845
page 60/108