Inter-Integrated Circuit (I2C) 1/2; Table 44. Iic_Sm_0; Table 45. Iic_Sm_1; Table 46. Iic_Sm_2 - ST STM32F2 Series User Manual

3.6.9

Inter-integrated circuit (I2C) 1/2

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
UM1845 - Rev 4
Table 44.
IIC_SM_0
Periodical read-back of configuration registers
End user
This method must be applied to I2C configuration registers.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 45.
IIC_SM_1
Protocol error signals
ST
I2C communication module embeds protocol error checks (like overrun, underrun, packet error etc.)
conceived to detect network-related abnormal conditions. These mechanisms are able anyway to
detect a marginal percentage of hardware random failures affecting the module itself.
Error flag raise and optional Interrupt Event generation
Depends on peripheral configuration (e.g. baud rate), refer to functional documentation
Permanent and Transient
None
Depends on implementation
Continuous
Not needed
IIC_SM_2: Information redundancy techniques on messages
Adoption of SMBus option grants the activation of more efficient protocol-level hardware checks like
CRC-8 packet protection
Table 46.
IIC_SM_2
Information redundancy techniques on messages
End user
Description of hardware and software diagnostics
IIC_SM_0
IIC_SM_1
IIC_SM_2
UM1845
Section 3.6.5
page 36/108