Debug; Table 91. Dbg_Sm_0 - ST STM32F2 Series User Manual

3.6.21

Debug

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations None
UM1845 - Rev 4
Table 91. DBG_SM_0
DBG_SM_0
Independent watchdog
ST
The debug unintentional activation due to hardware random fault results in the massive disturbance
of CPU operations, leading to intervention of the independent watchdog or alternately, the other
system watchdog WWGDG or an external one
Reset signal generation
Depends on implementation (watchdog timeout interval)
Permanent
None
Depends on implementation
Continuous
Not needed
CPU_SM_1: control flow monitoring in application software
Description of hardware and software diagnostics
UM1845
page 62/108