Table 7. Cpu_Sm_2; Table 8. Cpu_Sm_3 - ST STM32F2 Series User Manual

SM CODE
Fault detection time
Addressed fault model
Dependency on MCU
configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known
limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU
configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known
limitations
SM CODE
Description
Ownership
Detailed implementation
UM1845 - Rev 4
CPU_SM_1
Depends on implementation. Higher value is fixed by watchdog timeout interval.
Permanent and Transient
None
Depends on implementation
Continuous
NA
CPU_SM_0: periodical core self-test software
-
Table 7.
CPU_SM_2
Double computation in application software
End user
A timing redundancy for safety-related computation is considered to detect transient faults affecting the
® ®
Arm Cortex -M3 CPU subparts devoted to mathematical computations and data access.
The guidelines for the implementation of the method are the following:
• The requirement needs be applied only to safety-relevant computation, which in case of wrong
result could interfere with the system safety functions. Such computation must be therefore carefully
identified in the original application software source code
• Both mathematical operation and comparison are intended as computation.
• The redundant computation for mathematical computation is implemented by using copies of the
original data for second computation, and by using an equivalent formula if possible
Depends on implementation
Depends on implementation
Transient
None
Depends on implementation
Continuous
Not needed
CPU_SM_0: periodical core self-test software
End user is responsible to carefully avoid that the intervention of optimization features of the used
compiler removes timing redundancies introduced according to this condition of use
Table 8.
CPU_SM_3
® ®
Arm Cortex -M3 HardFault exceptions
ST
HardFault exception raise is an intrinsic safety mechanism implemented in Arm
mainly devoted to intercept systematic faults due to software limitations or error in software design
(causing for example execution of undefined operations, unaligned address access). This safety
mechanism is also able to detect hardware random faults inside the CPU bringing to such described
abnormal operations
Description of hardware and software diagnostics
CPU_SM_2
CPU_SM_3
UM1845
® ®
Cortex -M3 core,
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