Advanced, General And Low-Power Timers Tim1/2/3/4/5/8/9/10/11/12/13/14; Table 67. Atim_Sm_0; Table 68. Atim_Sm_1 - ST STM32F2 Series User Manual

3.6.15

Advanced, general and low-power timers TIM1/2/3/4/5/8/9/10/11/12/13/14

Note: As the timers are equipped with many different channels, each independent from the others, and possibly
programmed to realize different features, the safety mechanism is selected individually for each channel.
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations Refer to NVIC_SM_0
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU
configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
UM1845 - Rev 4
Table 67.
ATIM_SM_0
Periodical read-back of configuration registers
End user
This method must be applied to advanced, general and low-power timers
TIM1/2/3/4/5/8/9/10/11/12/13/14 configuration registers.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 68.
ATIM_SM_1
1oo2 for counting timers
End user
This method implements via software a 1oo2 scheme between two counting resources.
The guidelines for the implementation of the method are the following:
• Two timers are programmed with same time base or frequency.
• In case of timer use as a time base: use in the application software one of the timer as time base
source, and the other one just for check. Coherence check for the 1oo2 is done at application level,
comparing two counters values each time the timer value is used to affect safety function.
• In case of interrupt generation usage: use the first timer as main interrupt source for the service
routines, and use the second timer as a "reference" to be checked at the initial of interrupt routine
Depends on implementation
Depends on implementation
Permanent and Transient
None
Depends on implementation
On demand
Not needed
CPU_SM_0: periodical core self-test software
Description of hardware and software diagnostics
ATIM_SM_0
ATIM_SM_1
UM1845
Section 3.6.5
page 49/108