Hash Processor (Hash); Table 110. Hash_Sm_0; Table 111. Hash_Sm_1 - ST STM32F2 Series User Manual

3.6.29

HASH processor (HASH)

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations -
Note: Hardware random failures consequences on potential security features violations are not analyzed in this
manual.
UM1845 - Rev 4
Table 110. HASH_SM_0
HASH_SM_0
Periodical read-back of HASH configuration registers
End user
This method must be applied to HASH configuration registers.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
HASH module available only on specific part numbers
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 111. HASH_SM_1
HASH_SM_1
HASH processing collateral detection
ST
Message digest computation performed by HASH module is composed by several data
manipulations and checks. A major part of the hardware random failures affecting HASH module
will lead to algorithm violations/errors, and so to decoding errors on the receiver side
Several error condition can happens, check functional documentation
Depends on peripheral configuration
Permanent and Transient
HASH module available only on specific part numbers
Depends on implementation
Continuous
N/A
HASH_SM_0: periodical read-back of HASH configuration registers
CPU_SM_0: periodical core self-test software
Description of hardware and software diagnostics
UM1845
Section 3.6.5
page 74/108