Video Data Output Modes - Basler L100k User Manual

2.5.5 Video Data Output Modes

series cameras can operate in Single 10 Bit, Single 8 Bit, Dual 10 Bit, or Dual 8 Bit output
L100
k
mode. These modes are described in detail in this section .
Operation in Single 10 Bit or Single 8 Bit Output Mode
(L101k, L103k and L104k)
In Single 10 Bit mode, the pixel clock operates at 20 / 40 / 62.5 MHz for the L101
respectively. On each clock cycle, the camera transmits 10 bits of pixel data, a line valid bit and a
data valid bit. The assignment of the bits is shown in Table 2-3.
The pixel clock is used to time data sampling and transmission. As shown in Figures 2-4 and 2-6,
the camera samples and transmits data on each falling edge of the pixel clock.
The line valid bit indicates that a valid line is being transmitted. Pixel data is only valid when the
line valid bit is high. The data valid bit is not used in this mode and should be ignored.
Operation in Single 8 Bit mode is similar to Single 10 Bit mode except that the two least significant
bits output from each ADC are dropped and only 8 bits of data per pixel is transmitted.
The data sequence outlined below, along with Figures 2-4 and 2-6, describe what is
happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
Video Data Sequence
When the camera is not transmitting valid data, the line valid bit sent on each cycle of the pixel
clock will be low. Once the camera has completed line acquisition, it will begin to send valid data:
• On the pixel clock cycle where line data transmission begins, the line valid bit will become
high. Ten of the bits transmitted during this clock cycle will contain the data for pixel number
one.
• On the second cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmit-
ted during this clock cycle will contain the data for pixel number two.
• On the third cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted
during this clock cycle will contain the data for pixel number three.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
1024 cycles for cameras with a 1K sensor and 2048 cycles for cameras with a 2K sensor.)
• After all of the pixels have been transmitted, the line valid bit will become low indicating that
valid line data is no longer being transmitted.
Figures 2-4 and 2-5 show the data sequence when the camera is operating in edge-controlled or
level-controlled exposure mode. Figure 2-6 shows the data sequence when the camera is
operating in programmable exposure mode.
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The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
BASLER L100
k Series
DRAFT
1
Camera Interface
/ L103 / L104
k k k
2-9