L800K Video Data Output Modes; Operation In Single Output Mode (10 Or 8 Bit Depth) - Basler L800k User Manual

Camera Interface

2.5.5 L800k Video Data Output Modes

cameras can operate in single 10 bit, single 8 bit, dual 10 bit, dual 8 bit, dual separated 10
L800
k
bit or dual separated 8 bit output mode.

2.5.5.1 Operation in Single Output Mode (10 or 8 Bit Depth)

In single 10 bit mode, the pixel clock operates at 20 / 40 / 60 MHz for the L801k / L802k / L803k
respectively. On each clock cycle, the camera transmits data for one pixel at 10 bit depth, a line
valid bit and a data valid bit. The assignment of the bits is shown in Table 2-3 on page 2-10.
The pixel clock is used to time data sampling and transmission. As shown in Figures
the camera samples and transmits data on each rising edge of the pixel clock.
The line valid bit indicates that a valid line is being transmitted and the data valid bit indicates that
valid pixel data is being transmitted. Pixel data is only valid when the line valid and data valid bits
are both high.
Operation in single 8 bit mode is similar to single 10 bit mode except that the two least significant
bits are dropped and only 8 bits of data per pixel is transmitted.
The data sequence outlined below, along with Figures
is happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
Video Data Sequence
When the camera is not transmitting valid data, the line valid and data valid bits transmitted on
each cycle of the pixel clock will be low. Once the camera has completed line acquisition, it will
begin to send valid data:
• On the clock cycle where pixel data transmission begins, the line valid and data valid bits will
become high. Ten of the bits transmitted during this clock cycle will contain the data for pixel
number one.
• On the second cycle of the pixel clock, the line valid and data valid bits will be high. Ten of the
bits transmitted during this clock cycle will contain the data for pixel number two.
• On the third cycle of the pixel clock, the line valid and data valid bits will be high. Ten of the
bits transmitted during this clock cycle will contain the data for pixel number three.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
8160 cycles.
• After all of the pixels have been transmitted, the line valid and data valid bits will become low
indicating that valid pixel data is no longer being transmitted.
Figure 2-4 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and figure
in programmable exposure mode.
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1
The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
2-12
Draft
1
2
)
2-5 shows the data sequence when the camera is operating
2-4 and 2-5,
2-4 and 2-5, describes what
BASLER L800
k