Video Data Output Modes - Basler A202K Manual

2.5.4.2 Video Data Output Modes

The A202 can output pixel data in either a Dual 10 Bit, or a Dual 8 Bit output mode. These modes
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are described in detail below.
Operation in Dual 10 Bit or Dual 8 Bit Output Mode
In Dual 10 Bit mode, the pixel clock operates at 40 MHz. On each clock cycle, the camera
transmits data for two pixels at 10 bit depth, a frame valid bit, and a line valid bit. The assignment
of the bits is shown in Table 2-3.
The pixel clock is used to time data sampling and transmission. As shown in Figures 2-4 and 2-5,
the camera samples and transmits data on each falling edge of the pixel clock.
The frame valid bit indicates that a valid frame is being transmitted.
The line valid bit indicates that a valid line is being transmitted. Pixel data is only valid when the
frame valid bit and the line valid bit are both high.
Operation in Dual 8 Bit mode is similar to Dual 10 Bit mode except that the two least significant
bits output from each ADC are dropped and only 8 bits of data per pixel is transmitted.
The data sequence outlined below, along with Figures 2-4 and 2-5, describe what is
happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
Video Data Sequence
When the camera is not transmitting valid data, the frame valid and line valid bits sent on each
cycle of the pixel clock will be low. Once the camera has completed frame acquisition, it will begin
to send valid data:
• On the pixel clock cycle where frame data transmission begins, the frame valid bit will
become high.
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Ten of the bits transmitted during this clock cycle will contain the data for pixel
number one in line one and ten of the bits will contain data for pixel number two in line one.
• On the next cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted
during this clock cycle will contain the data for pixel number three in line one and ten of the
bits will contain data for pixel number four in line one.
• On the next cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmitted
during this clock cycle will contain the data for pixel number five in line one and ten of the bits
will contain data for pixel number six in line one.
• This pattern will continue until all of the pixel data for line one has been transmitted.
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1 The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
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BASLER A202
DRAFT
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Camera Interface
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