Basler L100k User Manual page 28

Camera Interface
Operation in Dual 10 Bit or Dual 8 Bit Output Mode (L103k and L104k only)
In Dual 10 Bit mode, the pixel clock operates at 20 MHz for the L103
On each clock cycle, the camera transmits a line valid bit, a data valid bit and ten bits of data for
two pixels. The assignment of the bits is shown in Table 2-3.
The pixel clock is used to time data sampling and transmission. As shown in Figures 2-9 and 2-
10, the camera samples and transmits data on each falling edge of the pixel clock.
The line valid bit indicates that a valid line is being transmitted. Pixel data is only valid when the
line valid bit is high. The data valid bit is not used in this mode. It is always high and should be
ignored.
Operation in Dual 8 Bit mode is similar to Dual 10 Bit mode except that the two least significant
bits output from each ADC are dropped and only 8 bits of data per pixel is transmitted.
The data sequence outlined below, along with Figures 2-9 and 2-10, describe what
is happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
Video Data Sequence
When the camera is not transmitting valid data, the line valid bit sent on each cycle of the pixel
clock will be low. Once the camera has completed line acquisition, it will begin to send valid data:
• On the pixel clock cycle where line data transmission begins, the line valid bit will become
high. Ten of the bits transmitted during this clock cycle will contain the data for pixel number
one and ten of the bits will contain data for pixel number two.
• On the second cycle of the pixel clock, the line valid bit will be high. Ten of the bits transmit-
ted during this clock cycle will contain the data for pixel number three and ten of the bits will
contain data for pixel number four.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
512 cycles for cameras with a 1K sensor and 1024 cycles for cameras with a 2K sensor.)
• After all of the pixels have been transmitted, the line valid bit will become low indicating that
valid line data is no longer being transmitted.
Figure 2-9 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and Figure 2-10 shows the data sequence when the camera is
operating in programmable exposure mode.
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1
The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
2-14
DRAFT
1
and 31.25 MHz for the L104
k
BASLER L100
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k
k Series