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Programming
Monitoring the Instrument
Enabling register bits with masks
Several masks are available which you can use to enable or disable
individual bits in each register. For example, you can disable the Hard-
copy bit in the OPERation Status Register so that even though it goes
high, it can never set the summary bit in the status byte high.
Use the *SRE common command to set or query the mask for the Sta-
tus Byte Register.
The masks for the OPERation Status and QUEStionable Status registers
are set and queried using the STATus subsystem's ENABle commands.
Use the *ESE common command to set or query the mask for the
Standard Event Status Register.
The *CLS common command clears all event registers and all queues
except the output queue. If *CLS is sent immediately following a pro-
gram message terminator, the output queue is also cleared. In addition,
the request for the *OPC bit is also cleared.
For example, suppose your application requires an interrupt whenever
any type of error occurs. The error related bits in the Standard Event
Status Register are bits 2 through 5. The sum of the decimal weights of
these bits is 60. Therefore, you can enable any of these bits to generate
the summary bit by sending the *ESE 60 command.
Whenever an error occurs, it sets one of these bits in the Standard
Event Status Register. Because the bits are all enabled, a summary bit
is generated to set bit 5 in the Status Byte Register.
If bit 5 (ESB) in the Status Byte Register is enabled (via the *SRE
command), an SRQ service request interrupt is sent to the external
computer.
Standard Event Status Register bits that are not enabled still respond
to their corresponding conditions (that is, they are set if the corre-
sponding event occurs). However, because they are not enabled, they
do not generate a summary bit to the Status Byte Register.
3-21
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