Interrupt Handling; Hawk Mpic; Table 1-12. Hawk Mpic Interrupt Assignments - Motorola MVME5100 Programmer's Reference Manual

INTERRUPT HANDLING

The interrupt architecture for the MVME5100 is fully compliant with the
PowerPlus II internal programming configuration. The following sections
further describe MVME5100 interrupt related issues.

Hawk MPIC

The Hawk MPIC interrupt assignment for the MVME5100 is shown in the
following table:

Table 1-12. Hawk MPIC Interrupt Assignments

MPIC Edge/
IRQ Level
IRQ0 Level
IRQ1 Level
IRQ2 Level
IRQ3 Level
IRQ4 Level
IRQ5 Level
IRQ6 Level
IRQ7 Level
IRQ8 Level
IRQ9 Level
IRQ10 Level
IRQ11 Level
IRQ12 Level
IRQ13 Level
IRQ14 Level
IRQ15 Level
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Polarity
High PIB (8259) from IPMC761 in PMC Slot 1
Low TL16C550 UART Serial Port 1,2
Low PCI-Ethernet Device Port 1 (Front panel or P2)
Low Hawk WDT1O_L, WDT2O_L
Low Thermal Alarm output (TOUT) of
Dallas Semi DS1621
Low PCI-VME INT 0 (Universe LINT0#)
Low PCI-VME INT 1 (Universe LINT1#)
Low PCI-VME INT 2 (Universe LINT2#)
Low PCI-VME INT 3 (Universe LINT3#)
Low PCI-PMC1 INTA#, PMC2 INTB#, PCIX INTA#
Low PCI-PMC1 INTB#, PMC2 INTC#, PCIX INTB#
Low PCI-PMC1 INTC#, PMC2 INTD#, PCIX INTC#
Low PCI-PMC1 INTD#, PMC2 INTA#, PCIX INTD#
Low PCI-Ethernet Device Port 2 (Front panel only)
Low ABORT_L
Low RTC - Alarm
INTERRUPT HANDLING
Interrupt Source
1
Notes
3
1,4
5
6
2
2
2
2
1
1-19