Pci Arbiter; Table 2-9. Pci Arbiter Pin Description - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2

PCI Arbiter

Pin Name
PARBI0
PARBI1
PARBI2
PARBI3
PARBI4
PARBI5
PARBI6
PARBO0
PARBO1
PARBO2
PARBO3
PARBO4
PARBO5
PARBO6
2-34
Generating PCI Interrupt Acknowledge Cycles
Performing a read from the PIACK register will initiate a single PCI
Interrupt Acknowledge cycle. Any single byte or combination of bytes
may be read from, and the actual byte enable pattern used during the read
will be passed on to the PCI bus. Upon completion of the PCI interrupt
acknowledge cycle, the PHB will present the resulting vector information
obtained from the PCI bus as read data.
The Hawk's internal PCI arbiter supports up to 8 PCI masters. This
includes Hawk and 7 other external PCI masters. The arbiter can be
configured to be enabled or disabled at reset time by strapping the rd[9] bit
either high for enabled or low for disabled.
its function for both modes.

Table 2-9. PCI Arbiter Pin Description

Pin Reset
Type
Direction
Input - - Input
Input - - Input
Input - - Input
Input - - Input
Input - - Input
Input - - Input
Input - - Input
Output Tristate Output
Output Tristate Output
Output Tristate Output
Output Tristate Output
Output Tristate Output
Output Tristate Output
Output Tristate Output
Table 2-9
Internal Arbiter
Function
ext req0_
ext req1_
ext req2_
ext_req3_
ext_req4_
ext req5_
ext req6_
ext gnt0_
ext gnt1_
ext gnt2_
ext gnt3_
ext gnt4_
ext gnt5_
ext gnt6_
Computer Group Literature Center Web Site
describes the pins and
External Arbiter
Direction Function
input HAWK gnt_
Input NA
Input NA
Input NA
Input NA
Input NA
Input NA
Output HAWK req_
Output NA
Output NA
Output NA
Output NA
Output NA
Output NA