Motorola MVME5100 Programmer's Reference Manual page 72

The device that has its IDSEL connected to the address bit being asserted
is selected for a configuration cycle. The PHB decodes the Device Number
to determine which of the upper address lines to assert. The decoding of
the five-bit Device Number is show as follows:
The Bus Number determines which bus is the target for the configuration
read cycle. The PHB will always host PCI bus #0. Accesses that are to be
performed on the PCI bus connected to the PHB must have zero
programmed into the Bus Number. If the configuration access is targeted
for another PCI bus, then that bus number should be programmed into the
Bus Number field. The PHB will detect a non-zero field and convert the
transaction to a Type 1 Configuration cycle.
Generating PCI Special Cycles
The PHB supports the method stated in PCI Local Bus Specification 2.1
using Configuration Mechanism #1 to generate special cycles. To prime
the PHB for a special cycle, the host processor must write a 32 bit value to
the CONFIG_ADDRESS register. The contents of the write are defined
later in this chapter under the CONFIG_ADDRESS register definition.
After the write to CONFIG_ADDRESS has been accomplished, the next
write to the CONFIG_DATA register causes the PHB to generate a special
cycle on the PCI bus. The write data is driven onto AD[31:0] during the
special cycle's data phase.
http://www.motorola.com/computer/literature
Device Number Address Bit
00000
00001 - 01010
01011
01100
(etc.)
11101
11110
11111
Functional Description
AD31
All Zeros
AD11
AD12
(etc.)
AD29
AD30
All Zeros
2
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