I2C Receiver Data Register; Sdram Enable And Size Register (Blocks E,F,G,H) - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
2
C Receiver Data Register
I
Address
Bit
3
Name
Operation
Reset
I2_DATARD

SDRAM Enable and Size Register (Blocks E,F,G,H)

Address
Bit
Name
Operation
Reset
3-66
READ ZERO READ ZERO
X
The I2_DATARD contains the receive byte for I
transfers. During I
receive byte must be read before any new one can be brough in.
A read of this register will automatically clear the i2_datin bit in
2
the I C Status Register.
Writes to this register must be enveloped by a period of time in which no
accesses to SDRAM occur. The requirements of the envelope are that all
SDRAM accesses must have completed before the write starts and none
should begin until after the write is done. A simple way to do this is to
perform at least two read accesses to this or another register before and
after the write.
Additionally, sometime during the envelope, before or after the write, all
of the SDRAMs' open pages must be closed and the Hawk's open page
tracker reset. The way to do this is to allow enough time for at least one
SDRAM refresh to occur by waiting for the 32-bit Counter (see section
further on) to increment at least 100 times. The wait period needs to
happen during the envelope.
$FEF800B0
READ ZERO
X X
2
C sequential read operation, the current
$FEF800C0
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I2_DATARD
READ
0 PL
2
C data