I2C Transmitter Data Register - Motorola MVME5100 Programmer's Reference Manual

i2_ackin
i2_cmplt
2
I C Transmitter Data Register
Address
Bit
Name
Operation
READ ZERO
Reset
X
I2_DATAWR The I2_DATAWR contains the transmit byte for I
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Register, and further writes to the I
be allowed until after the I
2
from the I C Status Register will clear this bit.
This bit is set if the addressed slave device is acknowledged to
either a start sequence or data writes from the I
controller and cleared otherwise. The I
automatically clear this bit at the beginning of the next valid I
operation.
This bit is set after the I
completed the requested I
beginning of every valid I
power-up.
$FEF800A8
READ ZERO
X
transfers. If a value is written to I2_DATAWR when the i2_start
and i2_enbl bits in the I
sequence is generated immediately followed by the transmission
of the contents of the I2_DATAWR to the responding slave
device. The I2_DATAWR[24:30] is the device address, and the
I2_DATAWR[31] is the WR/RD bit (0=WRite, 1=ReaD). After
a start sequence with I2_DATAWR[31]=0, subsequent writes to
2
the I C Transmitter Data Register will cause the contents of
I2_DATAWR to be transmitted to the responding slave device.
After a start sequence with I2_DATAWR[31]=1, subsequent
2
writes to the I C Transmitter Data Register (data=don't care)
will cause the responding slave device to transmit data to the I
Receiver Data Register. If a value is written to I2_DATAWR
(data=don't care) when the i2_stop and i2_enbl bits in the I
Control Register are set, a stop sequence is generated.
Programming Model
2
C Control Register will not
2
C Status Register is read. A read
2
C master controller will
2
C master controller has successfully
2
C operation and cleared at the
2
C operation. This bit is also set after
READ ZERO
X
2
C Control Register are set, a start
2
C master
2
C
I2_DATAWR
READ/WRITE
0 PL
2
C data
2
C
2
C
3-65
3