Motorola MVME5100 Programmer's Reference Manual page 52

Table 2-4. PPC Master Read Ahead Options (Continued)
RXF RMF RAE
T T N
00 xx 1
xx 00 x
01 xx 1
xx 01 x
10 xx 1
xx 10 x
11 xx 1
xx 11 x
Upon completion of a prefetched read transaction, any residual read data
left within the PCI FIFO will be invalidated (discarded). The PHB does not
have a mechanism for snooping the PPC60x bus for transactions associated
with the prefetched read data within the PCI FIFO. Therefore, caution
should be exercised when using the prefetch option within coherent
memory space.
The PPC Master will never perform prefetch reads beyond the address
range mapped within the PCI Slave map decoders. As an example, assume
PHB has been programmed to respond to PCI address range $10000000
through $1001FFFF with an offset of $2000. The PPC Master will perform
its last read on the PPC60x bus at cache line address $3001FFFC or word
address $3001FFF8.
The PPC60x bus transfer types generated by the PPC Master depend on the
PCI command code and the INV/GBL bits in the PSATTx registers. The
GBL bit determines whether or not the GBL_ signal is asserted for all
portions of a transaction and is fully independent of the PCI command
code and INV bit. The following table shows the relationship between the
PCI command codes and the INV bit.
http://www.motorola.com/computer/literature
PCI Initial
Command Read Size
Read 4 cache lines
Read Line
Read Multiple
Read 4 cache lines
Read Line
Read Multiple
Read 4 cache lines
Read Line
Read Multiple
Read 4 cache lines
Read Line
Read Multiple
Functional Description
Subsequent
Continuation
Read Size
FIFO <= 0 FIFO >= 4
cache lines cache lines
FIFO <= 1 FIFO >= 4
cache line cache lines
FIFO <= 2 FIFO >= 4
cache lines cache lines
FIFO <= 3 FIFO >= 4
cache lines cache lines
2
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