Motorola MVME5100 Programmer's Reference Manual page 269

RESET and ABORT Switch
Revision ID Register
programmable DMA Controller
ROM
Block A Size Encodings
Block B Size Encoding
Flash 3-14
Flash A Base Address control bits
Flash A size encoding
Flash A Width control bit
Flash B Base Address control bits
Flash B Width control bit
Flash speeds of SMC
S
scrub counter
Scrub Write Enable control bit
Scrub/Refresh Register
SDRAM
block organization
connections (block diagram)
Operational Method for Sizing
registers initializing
sizing 3-76
speed attributes
speeds 3-7
SDRAM
Base Address/Enable
Base Register
Enable and Size Register
Speed Attributes Register
Serial Presence Detect (SPD)
Single Bit Error Counter
sizing SDRAM
SMC
I
32-Bit Counter
N
address parity
cache coherency
D
CLK Frequency Register
E
CSR Accesses
X
cycle types
data parity
IN-6
1-2
2-69
1-2
3-54
3-57
3-54
3-53
3-57
3-9
3-51
3-51
3-51
3-9
3-4
3-83
3-75
3-75
3-76
3-43
3-66
3-68
3-76
3-50
3-76
3-72
3-10
3-11
3-44
3-34
3-11
3-10
data transfers
ECC Control Register
Error Address Register
Error Logger Register
error logging
External Register Set
General Control Register
3-53 L2 cache support
refresh/scrub
ROM A Base/Size Register
3-56 ROM B Base/Size Register
ROM Speed Attributes Register
Scrub/Refresh Register
SDRAM
Base Address Register
Enable and Size Register
Speed Attributes Register
Vendor/Device Register
soft reset, MPIC
software considerations
Software Readable Header Register
SPD JEDEC standard definition
Speculative PCI Request
Spurious Vector Register
SRAM base address
status bit descriptions
Status Register
System Bus 1-4
System Controller Mode bit
System Memory
T
target initiated termination
TBEN Bit Register
Timer
Basecount Registers
Current Count Registers
Destination Registers
Frequency Register
Vector/Priority Registers
timing (ROM/Flash access)
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Index
3-9
3-45
3-51
3-49
3-13
3-34
3-39
3-11
3-34
3-53
3-56
3-58
3-51
3-43
3-41
3-68
3-39
4-4
3-74
1-16
1-6
2-46
2-116
3-35
3-38
1-13
1-13
1-6
2-24
1-16
2-118
2-117
2-120
2-116
2-119
3-19