Motorola MVME5100 Programmer's Reference Manual page 268

Master 2-10
Master, Bug Hog 2-14
Master, doing prefetched reads
Master, read ahead mode
parity 2-17
register map 2-67
registers 2-67
slave's role 2-7
to PCI address translation
write posting 2-9
PPC Arbiter
debug functions 2-16
parking modes 2-16
prioritization schemes
PPC Error
Address Register 2-83
Attribute Register - EATTR
Enable Register 2-78
Status Register 2-81
PPC Slave
Address (0,1 and 2) Registers
Address (3) Register
Address Register 2-89
Offset/Attribute Registers
PPC60x Data Parity 3-10
Prescaler Adjust Register
priority schemes, described
Processor Init Register 2-114
processor internal clock frequenc
Processor
Memory Map 1-4
PLL Configuration 1-5
Type Identification
Version Register (PVR)
memory domain 4-8
programming details 1-1,
programming ROM/Flash devices
PVR value 1-4
http://www.motorola.com/computer/literature
2-13
2-12
2-7
2-16
2-84
2-87
2-88
2-90
2-76
2-35
1-5
1-4
1-4
4-1
3-74
R
RAM
A BASE 3-43, 3-67
B BASE 3-43, 3-67
C BASE 3-43, 3-67
D BASE 3-43, 3-65, 3-66,
read ahead mode, PPC Master
Read/Write Checkbits control bit
refresh/scrub 3-34
register bit descriptions 3-38
register summary 3-36
registers
CLK Frequency 3-44
CONFIG_ADDRESS
CONFIG_DATA 2-107
End-of-Interrupt 2-126
External Source Destination
External Source Vector/Priority
Feature Reporting 2-111
General Purpose 2-94
Global Configuration
Hardware Control-Status Register
Header Type 2-99
Interprocessor Interrupt Dispatch
Interrupt Acknowledge
IPI Vector/Priority (MPIC)
MPIC 2-108
MPIC I/O Base Address
MPIC Memory Base
PCI
Inter
rupt Acknowledge
Slave Address 2-101
Slave Attribute
PHB-Detected Errors Destination
PPC
E
rror Address 2-83
Error Attribute
Error Enable 2-78
Error Status 2-81
Slave Address 2-89
Slave Offset/Attribute 2-88,
3-67
2-12
3-45
2-104
2-122
2-120
2-112
2-76
2-124
2-125
2-115
2-100
2-100
2-86
2-102
2-124
2-84
2-90
IN-5
I
N
D
E
X