Figure 1-1. Mvme5100 Block Diagram - Motorola MVME5100 Programmer's Reference Manual

The following block diagram illustrates the architecture of the
MVME5100 Single Board Computer.
L2 Cache
1M,2M
Processor
750 Max
Clock
Generator
http://www.motorola.com/computer/literature
Hawk Asic
System Memory Controller (SMC)
and PCI Host Bridge (PHB)
33 MHz 32/64-bit PCI Local Bus
TL16C550
UART
Ethernet 1 Ethernet 2
10/100TX 10/100TX
761 or PMC
VME P2

Figure 1-1. MVME5100 Block Diagram

Mezzanine SDRAM
32MB to 512MB
SDRAM
32MB to 512MB
RTC/NVRAM/WD
Hawk X-bus
VME Bridge
Universe 2
Buffers
HDR
VME P1
Introduction
System
Registers
TL16C550
UART/9pin
planar
FLASH
1MB to 17MB
M48T37V
1-3
1