Config_Address Register - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2

CONFIG_ADDRESS Register

2-104
will be four cache lines. This field is only applicable if
read-ahead has been enabled. The encoding of this field is
shown in the table above.
WXFT
00
01
10
11
WXFTx Write Any FIFO Threshold. This field is used by the
PHB to determine a FIFO threshold at which to start
writing data into local memory during any PCI write
transaction. Once the threshold is exceeded and the write
has begun, the PHB will continue to empty its FIFO until
it can no longer create a cache line. This field is only
applicable if write-posting has been enabled. The
encoding of this field is shown in the above table.
The PCI Slave Offset Registers (PSOFFx) contain offset information
associated with the mapping of PCI memory space to PPC memory space.
The field within the PSOFFx registers is defined as follows:
PSOFFx PCI Slave Offset. This register contains a 16-bit offset
that is added to the upper 16 bits of the PCI address to
determine the PPC address used for transfers from PCI to
the PPC bus. This offset allows PPC resources to reside at
addresses that would not normally be visible from PCI.
The description of the CONFIG_ADDRESS register is presented in three
perspectives: from the PCI bus, from the PPC Bus in Big-Endian mode,
and from the PPC bus in Little-Endian mode. Note that the view from the
PCI bus is purely conceptual, since there is no way to access the
CONFIG_ADDRESS register from the PCI bus.
Write FIFO Threshold
4 Cache lines
3 Cache lines
2 Cache lines
1 Cache lines
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