Processor Pll Configuration; L2 Cache; L2 Cache Sram Size; Cache Speed - Motorola MVME5100 Programmer's Reference Manual

Processor PLL Configuration

The processor internal clock frequency (core frequency) is a multiple of
the system bus frequency. The processor has four configuration pins,
PLL_CFG[0:3], for hardware strapping of the processor core frequency
between 2x and 8x the system bus frequency, in 0.5x steps.
The PLL configuration shall be dynamic at power-up and be dependent
upon the existence of a memory mezzanine attached to the host board.

L2 Cache

The MVME5100 incorporates an L2 cache using a 2-way, set-associative
tag memory located in the MPC7400 processor, with external direct-
mapped synchronous SRAMs for data storage. The external SRAMs are
accessed through a dedicated L2 cache port on the processor.

L2 Cache SRAM Size

The L2 cache port will support SRAM configurations of 1MB or 2MB.
The L2 cache size is defined by reading the Vital Product Data (VPD)
SROM and programming the L2SIZ bits in the processor's Cache Control
Register (L2CR).

Cache Speed

The MPC7400 cache port provides the clock for the synchronous SRAMs.
This clock is generated by dividing the processor core frequency.
Available core-to-cache dividers range from 1 to 4, in .5 steps.
The core-to-cache ratio is selected by reading the VPD SROM and
programming the L2CLK bits of the processor's Cache Control Register.

Flash Memory

The MVME5100 Flash memory characteristics are fully compatible with
those specified in the Hawk's specification for Flash Blocks
A and B.
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System Bus
1
1-5