Address Parity Error Log Register - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
swr_dpl
3
tdp
trp
trcd

Address Parity Error Log Register

Address
Bit
Name
Operation
Reset
apelog
ape_tt0-4
3-70
swr_dpl causes the SMC to always wait until four clocks after
the write command portion of a single write before allowing a
precharge to occur. This function may not be required. If such is
the case, swr_dpl can be cleared by software.
tdp determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Tdp parameter.
When tdp is 0, the minimum time provided for Tdp is 1 clock.
When tdp is 1, the minimum is 2 clocks.
trp determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Trp parameter.
When trp is 0, the minimum time provided for Trp is 2 clocks.
When trp is 1 the minimum is 3 clocks.
trcd determines the minimum number of clock cycles that the
SMC assumes the SDRAM requires to satisfy its Trcd
parameter. When trcd is 0, the minimum time provided for Trcd
is 2 clocks. When trcd is 1 the minimum is 3 clocks.
$FEF800E0
apelog is set when a parity error occurs on the PPC60x address
bus during any PPC60x address cycle (TS_ asserted to AACK_
asserted). It is cleared by writing a one to it or by power-up reset.
ape_tt is the value that was on the TT0-TT4 signals when the
apelog bit was set.
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READ ZERO
X