Pci/Ppc Contention Handling; Table 2-14. Wdtxcntl Programming - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Byte Lane Selection
KEY ENAB
/RES
0:7 8:15
No x
Yes No
Yes Yes
Yes Yes
Yes Yes

PCI/PPC Contention Handling

2-44

Table 2-14. WDTxCNTL Programming

RELOAD
16:23 24:31 Prescaler/
x x No Change
x x
RES/ENAB
No x
from data
x No
from data
Yes Yes
from data
The WDTxCNTL register will always become unarmed after the second
write regardless of byte lane selection. Reads may be performed at any
time from the WDTxCNTL register and will not affect the write arming
sequence.
The PHB has a mechanism that detects when there is a possible resource
contention problem (i.e. deadlock) as a result of overlapping PPC and PCI
initiated transactions. The PPC Slave, PCI Slave, and PCI Master
functions contain the logic needed to implement this feature.
Results
WDT
Counter
Enable
No Change
Update Update
from from
RELOAD
Update Update
from
bus RELOAD
Update Update
from
bus RELOAD
Update Update
from data
bus bus
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WDTxCNTL Register
RES/ENAB RELOAD
No Change No Change
No Change No Change
Update No Change
from data
bus
Update No Change
from data
bus
Update Update
from data from
bus
data bus