Interrupt Handling - Motorola MCP750 Installation And Use Manual

Operating Instructions
2

Interrupt Handling

2-6
PMC Slot (PCI mezzanine card)
The arbitration for these six bus mastering devices is provided by custom
onboard hardware. This arbiter implements a rotating priority scheme in
which the last master granted becomes the lowest priority. The order of
rotation is shown in the list above.
The Raven ASIC provides an MPIC Interrupt Controller to handle various
interrupt sources. It controls PHB (PCI Host Bridge) MPU/local bus
interface functions on the MCP750 as well as performing interrupt
handling. Sources of interrupts may be any of the following:
The Raven ASIC itself (timer interrupts or transfer error interrupts)
The processor (processor self-interrupts)
The Falcon chip set (memory error interrupts)
The PCI bus (interrupts from PCI devices)
The CPCI bus (interrupts from CPCI devices)
Power monitor interrupts
Watchdog timer interrupt
The ISA bus (interrupts from ISA devices)
For details on interrupt handling, refer to the MCP750 Series Single Board
Computer Programmer's Reference Guide (part number MCP750A/PG).
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