I2C Interface - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
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I C Interface
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3-22
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The ASIC has an I C (Inter-Integrated Circuit) two-wire serial interface
bus: serial clock line (SCL) and serial data line (SDA). This interface has
master-only capability and may be used to communicate the configuration
information to a slave I
interface is compatible with these devices, and the inclusion of a serial
EEPROM in the memory subsystem may be desirable. The EEPROM
could maintain the configuration information related to the memory
subsystem even when the power is removed from the system. Each slave
device connected to the I
address. The number of interfaces connected to the I
dependent on the bus capacitance limit of 400pF.
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For I C bus programming, the ASIC is the only master on the bus and the
serial EEPROM devices are all slaves. The I
addressing mode and transmits data one byte at a time in a serial fashion
with the most significant bit (MSB) being sent out first. Five registers are
required to perform the I
Clock Prescaler Register, I
Transmitter Data Register, and I
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The I C serial data (SDA) is an open-drain bi-directional line on which
data can be transferred at a rate up to 100 Kbits/s in the standard mode, or
up to 400 kbits/s in the fast mode. The I
programmable via I2_PRESCALE_VAL bits in the I
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Register. The I C clock frequency is determined by the following formula:
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I C CLOCK = SYSTEM CLOCK / (I2_PRESCALE_VAL+1) / 2
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The I C bus has the ability to perform byte write, page write, current
address read, random read, and sequential read operations.
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C device such as serial EEPROM. The I
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C bus is software addressable by a unique
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C bus data transfer operations. These are the I
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C Control Register, I
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C Receiver Data Register.
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C serial clock (SCL) is
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C
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C bus is solely
C bus supports 7-bit
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C Status Register, I
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C Clock Prescaler
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C
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C