Motorola MVME5100 Programmer's Reference Manual page 265

configuration
options on Hawk
registers
requirements on Hawk
type, as used by PHB
contention
between PCI and PPC
handling explained (PHB)
control bit
descriptions
core frequency
CSR
accesses to SMC
architecture of SMC
base address
reads and writes
CWF burst transfers, explained
cycle types 3-11
D
data, prefetched reads
data parity 2-17
data throughput,
PPC Slave to PCI Master
data transfer, PPC Master rates
decoder priorities
decoders
address PCI to PPC
PCI to PPC addressing
PPC to PCI
delayed transactions, PCI Slave
device selection
I
Disable Error Correction control bit
N
DRAM
D
connection diagram
enable bits
E
size control bits
X
IN-2
3-35
2-19
3-35
2-31
2-44
2-45
3-38
1-5
3-34
3-35
3-35
3-35
2-26
2-13
2-9
2-10
2-21
2-6
2-19
2-7
2-24
2-24
3-47
3-4
3-41
3-41
E
ECC
codes 3-86
Control Register 3-45
EEPROM 1-2
EEPROM access 3-76
endian conversion 2-38
End-of-Interrupt Registers
Error Address Register 3-51
error
correction 3-11
detection 3-11
handling 2-41
logging 3-13
notification and handling
reporting 3-12
Error Logger Register 3-49
Ethernet controller 1-8
Ethernet interfaces 1-2
exclusive access 2-29
Extended Features
Register 1 1-17
Register 2 1-18
External Register Set 3-34,
External Source Destination Registers
F
fast back-to-back transactions
Feature Reporting Register
features 2-1
FIFO
from PPC Slave to PCI Master
structure explained 2-4
with PCI Slave 2-26
Flash (see ROM/Flash) 3-14
Flash Memory 1-2
form factor 1-2
four-beat reads/writes 3-6
functional description
Hawk 2-4
SMC 3-6
FUSE signal 1-13
Computer Group Literature Center Web Site
Index
2-126
4-5
3-72
2-122
2-29
2-111
2-9