Table 3-18. Deriving Tras, Trp, Trcd And Trc Control Bit Values From Spd Information - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
3
Table 3-18. Deriving tras, trp, trcd and trc Control Bit Values from SPD
Control Bits
$FEF800D1
bits 2,3
(tras)
3-78
c. If a CAS latency of 2 is supported, check SPD byte 23 to
determine the CAS_latency _2 cycle time. If the CAS_latency_2
cycle time is less than or equal to the period of the system clock
then this block can operate with a CAS latency of 2. Otherwise
a CAS latency of 3 is all that is supported for this block.
If any block does not support a CAS latency of 2, then cl3 is to
be set. If all of the blocks support a CAS latency of 2, then the
cl3 bit is to be cleared.
Do not update the cl3 bit at this point. You will use the
information from this step later.
4. Determine the values to use for tras, trp, trcd, and trc
The values to use for tras, trp, trcd and trc can be obtained from
the SPD. The tras bits determine the minimum tRAS time produced
by the Hawk. The trp bit determines the minimum tRP time
produced by the Hawk, etc. Each set of bits should accommodate
the slowest block of SDRAM. The SPD parameters are specified in
nanoseconds and have to be converted to 60x clock periods for the
Hawk.
Use the following table to convert SPD bytes 27, 29 and 30 to the
correct values for tras, trp, trcd and trc.
Do not actually update these bits in the Hawk at this time. You will
use the information from this step later.
Information
Parameter Parameter Expressed
in CLK Periods
tRAS tRAS_CLK = tRAS/T
(SPD Byte (T = CLK Period
30)
in nanoseconds)
See Notes 1, 2 and 9
Possible Control Bit Values
0.0 < tRAS_CLK <= 4.0
4.0 < tRAS_CLK <=5.0
5.0 < tRAS_CLK <= 6.0
6.0 < tRAS_CLK <= 7.0
7.0 < tRAS_CLK
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tras =%00
tras =%01
tras =%10
tras =%11
Illegal