Transaction Ordering - Motorola MVME5100 Programmer's Reference Manual

Between PCI writes, the PPC Master will be taking PPC60x bus bandwidth
trying to empty write posted data, which will further hamper the ability of
the processor to complete its read transaction.
PHB offers an optional speculative PCI request mode that helps the
processor complete read cycles from PCI space. If a bridge lock resolution
cycle happens when the PPC Slave is hosting a compelled cycle, the PCI
Master will speculatively assert a request on the PCI bus. Sometime later
when the processor comes back and retries the compelled cycle, the results
of the PCI Master holding will increase the chance of the processor
successfully completing its cycle.
PCI speculative requesting will only be effective if the PCI arbiter will at
least some times consider the PHB to be a higher priority master than the
master performing the PPC60x bound write cycles. The PCI Master obeys
the PCI specification for benign requests and will unconditionally remove
a speculative request after 16 clocks.
The PHB considers the speculative PCI request mode to be the default
mode of operation. If this is not desired, then the speculative PCI request
mode can be disable by changing the SPRQ bit in the HCSR.

Transaction Ordering

All transactions will be completed on the destination bus in the same order
that they are completed on the originating bus. A read or a compelled write
transaction will force all previously issued write posted transactions to be
flushed from the FIFO. All write posted transfers will be completed before
a read or compelled write begins to ensure that all transfers are completed
in the order issued.
All PCI Configuration cycles intended for internal PHB registers will also
be delayed if PHB is busy so that control bits which may affect write
postings do not change until all write posted transactions have completed.
For the same reason all PPC60x write posted transfers will also be
completed before any access to the PHB PPC registers begins.
The PCI Local Bus Specification 2.1 states that posted write buffers in
both directions must be flushed before completing a read in either
direction.
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Functional Description
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